1. Technical Field
The present invention relates to an integrated circuit package allowing easy access to the backside of the device for the purpose of failure analysis and, more particularly, to integrated circuit packages having an exposed backside or removable plug.
2. Description of Related Art
Integrated circuit packages are commonly inspected in order to detect defects in the manufacture of the package and, in particular, the encapsulated die. The process of analyzing defective packages to discover the cause of the defects is commonly referred to in the semiconductor industry as "failure analysis." Advancements in the very large-scale integration ("VLSI") processing related to higher integration and multiple level metalization schemes have greatly limited the ability to perform conventional failure analysis from the topside of the die. The semiconductor industry's response to this problem has been the development of backside failure analysis techniques. Backside emission microscopy is one of the most popular failure analysis techniques presently used in the semiconductor industry.
Examples of methods for removing silicon from the backside of semiconductor devices are disclosed in U.S. Pat. No. 5,252,842 (Buck et al.), U.S. Pat. No. 5,064,498 (Miller), U.S. Pat. No. and 4,784,721 (Holmen et al.). All backside techniques require that the package be opened using a combination of chemical and mechanical processes. In many cases the silicon must also be thinned after removing any packaging material. Because silicon, and especially doped silicon, is not perfectly transparent to near IR wave lengths of light, the silicon die must also be thinned. The most popular technique for opening IC packages involves the use of a mechanical grinder. Such systems are costly (about $50,000 to $70,000 each) and also expose the device to mechanical damage that could render the device unsuitable for electrical failure analysis. In fact, both mechanical and chemical etches are prone to cause damage to the die by chipping it or cracking it, thus leaving the device useless for most failure analysis procedures.
Accordingly, a need exists for an integrated circuit package that allows for easy access for backside failure analysis. The backside accessibility should ideally be accomplished at minimum cost and with the minimum potential for collateral damage to the package die.